In the context of, but not limited to, point-to-point fully buffered DIMM (dual in-line memory module) memory sub-system to be abbreviated as FBDIMM, system clocking for the high-speed serial point-to-point links between devices is one of the most critical areas of design. Within the field of FBDIMM, there exist two generations of architecture which support two different memory types and have two different system clocking schemes. The first generation, which will be referred to as FBDIMM1, supports DDR2 Double Data Rate memory speeds and has a simple system clocking scheme where a single reference clock is distributed to all devices in the memory subsystem and each device is then responsible for generating local high-speed clocks and performing local clock recovery on high speed links. The second generation, which will be referred to as FBDIMM2, supports DDR3 Double Data Rate memory speeds and has a more advanced clocking scheme where transmitted serial data is accompanied by a forwarded clock which can be used to simplify clock and data recovery.
The device which is being used to generate and terminate serialized command and data local to the memory devices is called an Advanced Memory Buffer (AMB). Like in FBDIMM, there exist two generations of AMB where the first generation is referred to as AMB1and the second generation is referred to as AMB2, and they are used in FBDIMM1and FBDIMM2respectively.
In the case of AMB1, all devices in the system are provided with a reference clock that is twenty four (24) times lower in frequency then the data rate supported by the high-speed serial links in the system. Serial interfaces on the AMB are expected to generate high-speed clocks locally to recover data reliably via localized clock and data recovery in each serial data path. Through very tightly controlled PLL (Phase Locked Loop) bandwidth specifications in all the devices in the system, jitter budgets can be roughly controlled and local clock and data recovery blocks within the devices can function properly.
In the second generation of AMB, the AMB2is required to support significantly higher memory speeds and serial data rates than the AMB1. However, there is still an overlap in some of the speeds which are due to the fact that there is overlap in the speed supported by the respective DDR2 and DDR3 memories. A mechanism to improve jitter budgets was required in AMB2, and the resulting architecture requires that all devices in the system are provided a reference clock that is twenty four (24) times lower in frequency than the data rate supported by the high-speed serial links, just as in the AMB1. However, each AMB2device is also required to forward, coupled with a set of high-speed serial data, a forwarded clock that is only 2 times lower in frequency than the data rate. This forwarded clock should be generated from the same PLL that is used to clock the output data, and hence have a very similar spectral profile as the data. This important property can be used to relax local clock data recovery (CDR) performance specifications, and can be used to significantly reduce AMB power.
Typically, a single generation of AMB would only be required to support a single clocking scheme, since AMB1 would support DDR2 memory, and AMB2 would support DDR3 memory. However, since there is overlap in the existence of DDR2 and DDR3 memory in the market, it is highly desirable to develop a device that can support both DDR2 and DDR3 memories, thus increasing product volume and driving down product cost. Additionally, if this new class of hybrid AMB could also interface with first generation host controllers as well as second generation host controllers, this ultimate AMB would have the broadest market coverage, highest volume, and potentially the broadest customer acceptance.